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Altera Carrier for FMC, Arria-10™ GX1150

  • Single module, mid-size AMC (full-size optional)
  • Altera Arria-10 GX1150 in F1517 package
  • AMC Ports 4-11 are routed to FPGA per AMC.1, AMC.2 and AMC.4 (protocols such as PCIe, SRIO, 10GbE/40GbE, etc. are FPGA programmable)
  • AMC Ports 12-15 and 17-20 are routed to the FPGA
  • AMC FCLKA, TCLKA, TCLKB, TCLKC and TCLKD are routed
  • Clock jitter cleaner
  • 16 GB of DDR4 (dual bank, 64-bit)

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The AMC536 is based on the Altera Arria-10™ GX1150 FPGA in F1517 package and is compliant to AMC.1, AMC.2, AMC.3 and/or AMC.4 specifications.

The module routes all LA/HA/HB and 10 DP SERDES to the FMC slot.

The onboard, re-configurable FPGA interfaces directly to the AMC FCLKA and TCLKA-D via a Cross Bar Switch (CBS) MLVDS. It also has two banks of DDR4 (64-bit wide) giving 16 GB total memory. This allows for large buffer sizes to be stored during processing as well as for queuing the data to the host.

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 VIDEO: Intel FPGA solutions at VadaTech: This video introduces the advantages of using VadaTech to build your new products embedding Intel FPGA SoC.

 

Key Features
  • Single module, mid-size AMC (full-size optional)
  • Altera Arria-10 GX1150 in F1517 package
  • AMC Ports 4-11 are routed to FPGA per AMC.1, AMC.2 and AMC.4 (protocols such as PCIe, SRIO, 10GbE/40GbE, etc. are FPGA programmable)
  • AMC Ports 12-15 and 17-20 are routed to the FPGA
  • AMC FCLKA, TCLKA, TCLKB, TCLKC and TCLKD are routed
  • Clock jitter cleaner
  • 16 GB of DDR4 (dual bank, 64-bit)
Benefits
  • Dual Bank of 64-bit wide DDR4 memory allows larger buffer sizes while processing and queuing data to the host
  • Electrical, mechanical, software, and system-level expertise in house
  • Full system supply from industry leader
  • AS9100 and ISO9001 certified company
Specifications
Specifications

Block diagram

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