A/D & D/A

AMC FPGA A/D D/A

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AMC597

300 MHz to 6 GHz Octal Versatile Wideband Transceiver (MIMO), UltraScale™, AMC

  • Xilinx UltraScale™ XCKU115 FPGA
  • Octo complete transceiver signal chain solution
  • Four AD9371s or AD9375s on one module
  • Frequency range 300 MHz to 6 GHz
  • Tx synthesis bandwidth (BW) to 250 MHz
  • Rx bandwidth: 8 MHz to 100 MHz
  • Supports Time Division Duplex (TDD) and Frequency Division Duplex (FDD) operation
  • On-board clocking or external clock with multi-transceivers synchronization capability
  • Three banks of DDR4 for total 20 GB
View product AMC597 Data Sheet

AMC549

NEW

SOFI Carrier UltraScale+™

  • Serial Optimized FPGA Interface (SOFI) Carrier
  • Xilinx UltraScale+™ XCVU13P FPGA
  • Dual Tongue to allow additional x16 SERDES routing with x8 additional LVDS on Tongue two
  • Option for high-speed ADC/DAC (see SOFI catalogue) A/D & D/A (vadatech.com)
  • Single bank of DDR4 64-bit wide 8 GB Total
  • AMC Ports 4-11 are routed to FPGA per AMC.1, AMC.2 and AMC.4 (protocols such as PCIe, SRIO, 1/10/40GbE, etc. are FPGA programmable) with additional x16 SERDES on Tongue two
  • AMC FCLKA, TCLKA, TCLKB, TCLKC and TCLKD are routed
  • Clock Jitter cleaner
  • IPMI 2.0 compliant
View product AMC549 Data Sheet

AMC594

LEGACY

Dual ADC 8-bit @ up to 56 GSPS, 2 or 4 Channels, UltraScale™ XCVU190, AMC

  • Dual ADC 8-bit @ up to 56 GSPS
  • 2 x 56 or 4 x 28 GSPS channels
  • Xilinx UltraScale™ XCVU190 FPGA
  • 16 GB of DDR4 Memory (2 banks of 64-bit)
  • ADC is 65 nm CMOS process technology)
  • Double module, full-size
  • Calibration warning and over-range flags
  •  –3 dB analog input bandwidth nominally 15 GHz
  • Internal 14 GHz VCO/PLL per I/Q ADC pair
  • Differential analog input: 1 VPP
View product AMC594 Data Sheet

AMC562

FMC+ Carrier Zynq UltraScale+ FPGA, AMC

  • Xilinx UltraScale+ XCZU7EV FPGA
  • Double module, mid-size
  • FMC+ site
  • 8 GB of 64-bit wide DDR4 Memory (single bank) with ECC
  • SD Card (option)
  • 128 MB of Boot Flash
  • 64 GB of User Flash
  • Clock Jitter Cleaner
  • Zone 3 class D1.0 connector pinout per DESY specification
View product AMC562 Data Sheet

AMC589

Quad ADC @ 3 GSPS with Quad DAC @ 12 GSPS, UltraScale+™, AMC

  • Xilinx UltraScale+™ XCVU13P FPGA
  • Quad ADC 14-bit @ 3 GSPS (AD9208)
  • Quad DAC 16-bit @ 12 GSPS (AD9162 or AD9164)
  • Single bank of DDR4 Memory 64-bit wide
  • AMC Ports 4-11 are routed to FPGA per AMC.1, AMC.2 and AMC.4 (protocols such as PCIe, SRIO, 1/10/40GbE, etc. are FPGA programmable)
  • AMC FCLKA, TCLKA, TCLKB, TCLKC and TCLKD are routed
  • Clock Jitter cleaner
  • Option for Direct RF Clock sampling for the ADC/DAC
  • IPMI 2.0 compliant
View product AMC589 Data Sheet

AMC587

Dual ADC @ 6.4 GSPS and Dual DAC @ 12 GSPS, UltraScale+, AMC

  • Xilinx UltraScale+™ XCVU13P FPGA
  • Dual ADC 12-bit @ 10.4 GSPS or quad ADC at 5.2 GSPS with TI ADC12DJ5200  
  • Option for ADC12DJ3200 or ADC12DJ2700
  • Dual DAC 16-bit @ 12 GSPS (AD9162 or AD9164)
  • Single bank of 64-bit wide DDR4, 8 GB
  • AMC Ports 4-11 are routed to FPGA per AMC.1, AMC.2 and AMC.4 (protocols such as PCIe, SRIO, 1/10/40GbE, etc. are FPGA programmable)
  • AMC FCLKA, TCLKA, TCLKB, TCLKC and TCLKD are routed
  • Clock jitter cleaner
  • IPMI 2.0 compliant
View product AMC587 Data Sheet

AMC590

LEGACY

ADC 8-bit @ up to 56 GSPS, 1/2/4 Channel, UltraScale™ XCKU115, AMC

  • Xilinx UltraScale™ XCKU115 FPGA
  • 8-bit ADC at up to 56 GSPS
  • 1 x 56, 2 x 28 or 4 x 14 GSPS channel
  • 24 GB of DDR4 Memory (3 banks of 64-bit)
  • ADC is 65 nm CMOS process technology
  • Very low power consumption (5W for the ADC)
  • Single module, mid-size or full-size
  • Calibration warning and over-range flags
  •  –3 dB analog input bandwidth nominally 15 GHz
  • Internal 14 GHz VCO/PLL per I/Q ADC pair
  • Differential analog input: 1.0V PPD
View product AMC590 Data Sheet

AMC588

300 MHz to 6 GHz Octal Versatile Wideband Transceiver (MIMO), UltraScale+™, AMC

  • Xilinx UltraScale+™ XCVU13P FPGA
  • Octo complete transceiver signal chain solution
  • Four AD9371s or AD9375s on one module
  • Frequency range 300 MHz to 6 GHz
  • Tx synthesis bandwidth (BW) to 250 MHz
  • Rx bandwidth: 8 MHz to 100 MHz
  • Supports Time Division Duplex (TDD) and Frequency Division Duplex (FDD) operation
  • Onboard clocking or external clock with multi-transceivers synchronization capability
  • IPMI 2.0 compliant
View product AMC588 Data Sheet

AMC599

Dual ADC @ 6.4 GSPS and Dual DAC @ 12 GSPS, UltraScale, AMC

  • Xilinx UltraScale™ XCKU115 FPGA
  • Dual ADC 12-bit @ 10.4/6.4 GSPS or quad ADC @ 5.2/3.2 GSPS with TI ADC12DJ5200 or ADC12DJ3200
  • Option for ADC12DJ5200, ADC12DJ3200 or ADC12DJ2700
  • Dual DAC 16-bit @12 GSPS (AD9162 or AD9164)
  • Two banks of 64-bit wide and a single bank of 32-bit wide DDR4 for a total of 20 GB
  • AMC Ports 4-11 are routed to FPGA per AMC.1, AMC.2 and AMC.4 (protocols such as PCIe, SRIO, 1/10/40GbE, etc. are FPGA programmable)
  • AMC FCLKA, TCLKA, TCLKB, TCLKC and TCLKD are routed
  • Clock jitter cleaner
  • IPMI 2.0 compliant
View product AMC599 Data Sheet

AMC902

Analog Filter, Gain Control with Dual Conditioning, AMC

  • Dual analog IF input with programmable attenuator per channel
  • Filtered and amplified Analog IF output
  • Dual clock input with flexible routing to backplane
  • Attenuation configuration via Port 0 (GbE) or front panel serial port
  • Single-module mid-size (option for full-size)
View product AMC902 Data Sheet

MRT523

MTCA.4 RTM for AMC523, 12 Ch ADC 16-bit @ 125 MSPS

  • MicroTCA.4 RTM for the AMC523
  • Twelve channel ADC 16-bit @ 125 MSPS utilizing AD9653 device routed to AMC523
  • Two analog outputs from AMC523’s DACs Mezzanine
  • ADC and DAC signal routed through amezzanine
  • Three pairs of user defined digital I/O
  • Double module, mid-size (full-size optional)
View product MRT523 Data Sheet

MZ523C

LEGACY

Mezzanine for MRT523, 12 Channel Optical Detector

  • 12 optical detectors routed to mezzanine connector
  • Per channel programmable gain, bandwidth and AC/DC coupling
  • 0 μW to 160 μW optical input power
  • 1310 nm to 1650 nm input wavelength
  • Noise 4 x 10-4 of full scale at min gain
  • Linearity <1%
  • Gain programmable 0-57 dB
  • Sensitivity 0.7 W/A typical
  • Mezzanine module for MRT523
View product MZ523C Data Sheet

MZ523A

Mezzanine for MRT523, 12 Channel Passive Pass-through

  • Mezzanine module for MRT523
  • Routes 12 analog inputs, 2 digital outputs, input clock, trigger in/out, three pairs of user defined digital I/O from rear panel to mezzanine connectors
  • Direct connection on all analog channels, giving full performance of the ADC
  • RoHS compliant
View product MZ523A Data Sheet

MZ523B

Mezzanine for MRT523, 12 Channel Variable Gain

  • Mezzanine module for MRT523
  • Routes 12 analog inputs, 2 analog outputs and CLK IN from rear panel SMPM to mezzanine connector
  • Routes TRIG IN/OUT, user I/O routed from rear panel DensiShield to mezzanine connectors
  • Per channel AC/DC selection and programmable gain
  • RoHS compliant
View product MZ523B Data Sheet

AMC589C

Quad ADC @ 3 GSPS with Quad DAC @ 12 GSPS, UltraScale+™, AMC

  • Xilinx UltraScale+™ XCVU13P FPGA
  • Conduction cooled solution
  • Quad ADC 14-bit @ 3 GSPS (AD9208)
  • Quad DAC 16-bit @ 12 GSPS (AD9162 or AD9164)
  • Single bank of DDR4 64-bit wide 8 GB Total
  • AMC Ports 4-11 are routed to FPGA per AMC.1, AMC.2 and AMC.4 (protocols such as PCIe, SRIO, 1/10/40GbE, etc. are FPGA programmable)
  • AMC FCLKA, TCLKA, TCLKB, TCLKC and TCLKD are routed
  • Clock Jitter cleaner
  • Option for Direct RF Clock sampling for the ADC/DAC
  • IPMI 2.0 compliant
View product AMC589C Data Sheet

DAQ523

MTCA.4 Data Acquisition Sub-system, 12-Channel 16-bit, 125 MSPS

  • Complete Data Acquisition sub-system
  • Supported by DAQ Series™ data acquisition software
  • Twelve channel ADC 16-bit @ 125 MSPS using AD9653
  • Dual DAC 16-bit @ 250 MSPS using MAX5878
  • Xilinx Kintex-7 FPGA XC7K410T with 2 GB of DDR3 memory
  • Double module, mid-size (full-size optional) AMC and RTM, compliant to μTCA.4
  • Internal or external clock, Trig in/out configurable by software
View product DAQ523 Data Sheet

AMC598

Quad ADC @ 3 GSPS with Quad DAC @ 12 GSPS, Kintex UltraScale, AMC

  • Xilinx UltraScale™ XCKU115 FPGA
  • Quad ADC 14-bit @ 3 GSPS (AD9208) (Option for Octal ADC with no DAC)
  • Quad DAC channels 16-bit @ 12 GSPS (AD9162 or AD9164) (Option for Octal DAC with no ADC)
  • Two banks of 64-bit wide and a single bank of 32-bit wide DDR4 for a total of 20 GB
  • AMC Ports 4-11 are routed to FPGA per AMC.1, AMC.2 and AMC.4 (protocols such as PCIe, SRIO, 1/10/40GbE, etc. are FPGA programmable)
  • AMC FCLKA, TCLKA, TCLKB, TCLKC and TCLKD are routed
  • Clock Jitter cleaner
  • Option for Direct RF Clock sampling for the ADC/DAC
  • IPMI 2.0 compliant
View product AMC598 Data Sheet

AMC575

Zynq UltraScale+ RFSoC FPGA, Double AMC, MTCA.4

  • Xilinx UltraScale+ RFSoC XCZU29DR FPGA
  • 8 ADC and 16 DAC to the rear
  • 8 GB of 64-bit wide DDR4 Memory (single bank) with ECC to CPU
  • 8 GB of 64-bit wide DDR4 Memory (single bank to Fabric)
  • MPSoC with block RAM and UltraRAM
  • SD Card (option)
  • 128 MB of boot Flash
  • 64 GB of user Flash
  • Double module, mid-size, MTCA.4
View product AMC575 Data Sheet

MRT523B

MTCA.4 RTM for AMC523, 8 Channel ADC 16-bit @ 125 MSPS

  • Double module, mid-size (full-size optional)
  • MicroTCA.4 RTM for the AMC523
  • Eight channel ADC 16-bit @ 125 MSPS utilizing AD9653 device routed to AMC523 with front end attenuation
  • Two ADC inputs via Logarithmic Detector with attenuation
  • Two analog outputs from AMC523’s DACs Mezzanine
  • Digital I/O via LEMO style connectors
View product MRT523B Data Sheet

AMC591

LEGACY

ADC @ 56 GSPS, 2 or 4 Channel, UltraScale, AMC

  • Double module, mid-size or full-size
  • Xilinx UltraScale™ XCVU190 FPGA
  • ADC 8-bit @ up to dual 56 GSPS
  • 2 x 56 or 4 x 28 GSPS channels
  • ADC is 65 nm CMOS process technology
  • 16 GB of DDR4 Memory (2 banks of 64-bit)
  • Very low power consumption (5W for the ADC)
  • Calibration warning and over-range flags
  • –3 dB analog input bandwidth nominally 15 GHz
  • Internal 14 GHz VCO/PLL per I/Q ADC pair
  • Differential analog input: 1.0V PPD
  • Tongue 2 for additional SERDES
View product AMC591 Data Sheet

MRT576B

MTCA.4 RTM for AMC576

  • MicroTCA.4 RTM for the AMC576
  • 16 ADC and 16 DAC signals to rear (Zone three)
  • DC-coupled ADC inputs have low noise and programmable amplifiers.
  • DC-coupled DAC have output amplifiers
  • Trigger routed to rear panel (four trig in and two trig out)
  • 16 Programmable LED with 8 LVDS Input/Output 
View product MRT576B Data Sheet

AMC574

Xilinx Zynq® UltraScale+ RFSoC FPGA, Double-width AMC

  • Xilinx Zynq® UltraScale+ RFSoC XCZU29DR FPGA
  • 16 ADC/DAC to the front
  • 8 GB of 64-bit wide DDR4 Memory (single bank) with ECC to CPU
  • 8 GB of 64-bit wide DDR4 Memory (single bank to Fabric)
  • MPSoC with block RAM and UltraRAM
  • SD Card (option)
  • 128 MB of boot Flash
  • 64 GB of user Flash
  • Double module, mid-size
View product AMC574 Data Sheet

AMC573

Xilinx Zynq® UltraScale+ RFSoC FPGA, AMC

  • Xilinx Zynq® UltraScale+ RFSoC XCZU28DR FPGA
  • 8 ADC/DAC to the front
  • 8 GB of 64-bit wide DDR4 Memory (single bank) with ECC to CPU 8 GB of 64-bit wide DDR4 Memory (single bank to Fabric)
  • MPSoC with block RAM and UltraRAM
  • SD Card (option)
  • 128 MB of boot Flash
  • 64 GB of user Flash
View product AMC573 Data Sheet

AMC524

Quad ADC, 16-bit @ 125 MSPS, Dual DAC, Artix-7

  • Quad ADC 16-bit @ 125 MSPS (AD9653)
  • Dual DAC 12-bit @ 2.5 GSPS (DDS AD9915)
  • Artix-7 FPGA with dual banks of DDR3, 2 GB total
  • Conduction cooled version available
  • Internal, external or backplane clock with onboard Wideband PLL
  • AMC Ports 4-7 and 8-11 are routed to FPGA per AMC.1, AMC.2 and AMC.4 (PCIe, SRIO, XAUI, etc. are FPGA programmable)
  • Single module, mid-size per AMC.0
  • IPMI 2.0 compliant
View product AMC524 Data Sheet

AMC529

AMC Dual DAC 14-bit @ 5.7 GSPS Module

  • Dual DAC 14-bit @ 5.7 GSPS (AD9129), 2.85 GSPS direct RF synthesis
  • Conduction cooled version available
  • Single module, mid-size per AMC.0
  • Xilinx Virtex-7 690T FPGA in FFG-1761package
  • Triple bank QDR-II+ memory (432 Mb total) and 1GB DDR3
  • AMC Ports 4-11 are routed to FPGA per AMC.1, AMC.2 and AMC.4 (PCIe, SRIO, XAUI, etc. are FPGA programmable)
  • AMC Ports 12-15 and 17-20 optionally routed to the FPGA
  • Internal, external or backplane clock with onboard Wideband PLL
  • IPMI 2.0 compliant
View product AMC529 Data Sheet

AMC526

AMC Dual ADC, Virtex-7, 12-Bit @ 2.6 GSPS

  • Single module, mid-size per AMC.0
  • Conduction cooled version available
  • Dual ADC, 12-Bit @ 2.6 GSPS (AD9625) in single module, mid-size
  • Xilinx Virtex-7 690T FPGA in FFG-1761 package
  • Quad bank QDR-II+ memory (576 Mb total) and 1Gb DDR3
  • AMC Ports 4-11 are routed to FPGA per AMC.1, AMC.2 and AMC.4 (PCIe, SRIO, XAUI, etc. are FPGA programmable)
  • AMC Ports 12-15 and 17-20 optionally routed to the FPGA
  • Internal, external or backplane clock with onboard Wideband PLL
  • IPMI 2.0 compliant
View product AMC526 Data Sheet

AMC511

FPGA, Quad Channel ADC 180 MSPS

  • Four channel LTC2209 ADC 180 MSPS @ 16-bit resolution
  • Xilinx Virtex-5 FPGA in FF1136 package
  • PCIe x4 or x8, GbE (FPGA programmable)
  • Aurora/SRIO option on lanes 8 to 11 if the PCIe x8 is not utilized
View product AMC511 Data Sheet

AMC523

Dual DAC 16-bit @ 250 MSPS, Kintex-7, MTCA.4

  • Dual DAC 16-bit @ 250 MSPS utilizing MAX5878 device (user programmable for lower sampling rate)
  • Xilinx Kintex-7 FPGA XC7K410T in FFG900 package
  • Supported by DAQ Series™ data acquisition software
  • 2 GB of DDR3 memory
  • Internal clock or precision external clock from RTM/backplane/front panel clocks
  • Trig in/out configurable by software (external trigger via front or port 17)
  • x8 PCIe (or dual x4)
  • AMC FCLKA, TCLKA, TCLKB, TCLKC and TCLKD are routed
  • Quad SFP+ (up to 6.6 Gbps)
  • JTAG selectable front and backplane
View product AMC523 Data Sheet

MRT522

MTCA.4 RTM for AMC522

  • Double module, mid-size (full-size optional)
  • Two analog outputs from AMC522’s DACs via SSMC connectors
  • Eight analog inputs (AC or DC coupled) via SSMC connectors feeding on-board ADCs via programmable gain amplifiers JTAG interface port
  • Clocks and Trigger In/Out accessible via  Mini-display Port connectors
  • IPMI v2.0 compliant
View product MRT522 Data Sheet

AMC522

MTCA.4 AMC Dual DAC, 16-bit @ 250 MSPS

  • Dual channel DAC 16-bit @ 250 MSPS (MAX5878)
  • Compliant to MTCA.4, double module, mid-size (full-size optional) with rear I/O
  • Xilinx Kintex-7 FPGA
  • Dual PCIe x4 or PCIe x8
  • JTAG interface port
  • AMC.1, AMC.2, AMC.4 compliant (FPGA programmable)
  • IPMI v2.0 compliant
View product AMC522 Data Sheet

AMC520

AMC 10-channel ADC, MicroTCA.4

  • Double module AMC, compliant to μTCA.4
  • Ten channel of ADC with 125MSPS @ 16-bit resolution utilizing AD9268 device
  • Dual DAC with 250 MSPS @ 16-bit resolution utilizing MAX5878 device (this is user programmable for lower sampling rate)
  • Internal clock or precision external clock from RTM/backplane/front panel clocks
  • Trig in/out configurable by software (external trigger via front or port 17)
  • Backplane PCIe Dual x4 or x8/Dual GbE
  • Xilinx Virtex-6 FPGA in FF1759 package
  • Option for QDR-II+
  • AMC FCLKA, TCLKA, TCLKB, TCLKC and TCLKD are routed
  • Dual SFP+ (up to 6.6Gbps)
  • JTAG selectable front and backplane
  • AMC.1 and AMC.2 (FPGA programmable)
View product AMC520 Data Sheet

MRT520

MicroTCA.4 RTM for AMC520

  • MicroTCA.4 RTM for the AMC520
  • Two analog outputs from AMC520’s DACs via SSMC connectors
  • Ten analog inputs (AC or DC coupled) interfacing directly with AMC520’s ADC ICs via SSMC connectors
  • Twelve LVDS signals and three differential reference clock routing to AMC520’s FPGA
  • LVDS and reference clocks accessible via dual high density DensiShield connectors
  • Double module, mid-size (full-size optional)
  • RoHS compliant
View product MRT520 Data Sheet

AMC521

24 Channels ADC, Mixed Sampling Rate

  • Sixteen channel of TI ADS42JB69 ADC 16-bit @ 250 MSPS
  • Eight channel SAR TI ADS8568 ADC 16-bit @ 650 KSPS simultaneous
  • Interface to the FPGA via JESD204B
  • 24 LVDS for Clock/Trig and/or GPIO
  • Virtex-7 FPGA 415T or 690T in FFG1158
  • Internal/External clock
  • Clock Jitter Cleaner with Dual Loop PLLs
  • Trig In/Out
  • A/D input via SSMC connectors
View product AMC521 Data Sheet

AMC FPGA A/D D/A

( expand all )

AMC597

300 MHz to 6 GHz Octal Versatile Wideband Transceiver (MIMO), UltraScale™, AMC

AMC549

SOFI Carrier UltraScale+™

AMC594

Dual ADC 8-bit @ up to 56 GSPS, 2 or 4 Channels, UltraScale™ XCVU190, AMC

AMC562

FMC+ Carrier Zynq UltraScale+ FPGA, AMC

AMC589

Quad ADC @ 3 GSPS with Quad DAC @ 12 GSPS, UltraScale+™, AMC

AMC587

Dual ADC @ 6.4 GSPS and Dual DAC @ 12 GSPS, UltraScale+, AMC

AMC590

ADC 8-bit @ up to 56 GSPS, 1/2/4 Channel, UltraScale™ XCKU115, AMC

AMC588

300 MHz to 6 GHz Octal Versatile Wideband Transceiver (MIMO), UltraScale+™, AMC

AMC599

Dual ADC @ 6.4 GSPS and Dual DAC @ 12 GSPS, UltraScale, AMC

AMC902

Analog Filter, Gain Control with Dual Conditioning, AMC

MRT523

MTCA.4 RTM for AMC523, 12 Ch ADC 16-bit @ 125 MSPS

MZ523C

Mezzanine for MRT523, 12 Channel Optical Detector

MZ523A

Mezzanine for MRT523, 12 Channel Passive Pass-through

MZ523B

Mezzanine for MRT523, 12 Channel Variable Gain

AMC589C

Quad ADC @ 3 GSPS with Quad DAC @ 12 GSPS, UltraScale+™, AMC

DAQ523

MTCA.4 Data Acquisition Sub-system, 12-Channel 16-bit, 125 MSPS

AMC598

Quad ADC @ 3 GSPS with Quad DAC @ 12 GSPS, Kintex UltraScale, AMC

AMC575

Zynq UltraScale+ RFSoC FPGA, Double AMC, MTCA.4

MRT523B

MTCA.4 RTM for AMC523, 8 Channel ADC 16-bit @ 125 MSPS

AMC591

ADC @ 56 GSPS, 2 or 4 Channel, UltraScale, AMC

MRT576B

MTCA.4 RTM for AMC576

AMC574

Xilinx Zynq® UltraScale+ RFSoC FPGA, Double-width AMC

AMC573

Xilinx Zynq® UltraScale+ RFSoC FPGA, AMC

AMC524

Quad ADC, 16-bit @ 125 MSPS, Dual DAC, Artix-7

AMC529

AMC Dual DAC 14-bit @ 5.7 GSPS Module

AMC526

AMC Dual ADC, Virtex-7, 12-Bit @ 2.6 GSPS

AMC511

FPGA, Quad Channel ADC 180 MSPS

AMC523

Dual DAC 16-bit @ 250 MSPS, Kintex-7, MTCA.4

MRT522

MTCA.4 RTM for AMC522

AMC522

MTCA.4 AMC Dual DAC, 16-bit @ 250 MSPS

AMC520

AMC 10-channel ADC, MicroTCA.4

MRT520

MicroTCA.4 RTM for AMC520

AMC521

24 Channels ADC, Mixed Sampling Rate

MicroTCA.4 AD/DA

( close )

MRT523

MTCA.4 RTM for AMC523, 12 Ch ADC 16-bit @ 125 MSPS

  • MicroTCA.4 RTM for the AMC523
  • Twelve channel ADC 16-bit @ 125 MSPS utilizing AD9653 device routed to AMC523
  • Two analog outputs from AMC523’s DACs Mezzanine
  • ADC and DAC signal routed through amezzanine
  • Three pairs of user defined digital I/O
  • Double module, mid-size (full-size optional)
View product MRT523 Data Sheet

AMC523

Dual DAC 16-bit @ 250 MSPS, Kintex-7, MTCA.4

  • Dual DAC 16-bit @ 250 MSPS utilizing MAX5878 device (user programmable for lower sampling rate)
  • Xilinx Kintex-7 FPGA XC7K410T in FFG900 package
  • Supported by DAQ Series™ data acquisition software
  • 2 GB of DDR3 memory
  • Internal clock or precision external clock from RTM/backplane/front panel clocks
  • Trig in/out configurable by software (external trigger via front or port 17)
  • x8 PCIe (or dual x4)
  • AMC FCLKA, TCLKA, TCLKB, TCLKC and TCLKD are routed
  • Quad SFP+ (up to 6.6 Gbps)
  • JTAG selectable front and backplane
View product AMC523 Data Sheet

MRT575A

MTCA.4 RTM for AMC575, Passive

  • MicroTCA.4 RTM for the AMC575
  • 8 ADC and 16 DAC signals routed to rear panel
  • Clock/trigger routed to rear panel
View product MRT575A Data Sheet

MRT566A

MTCA.4 RTM for AMC566

  • MicroTCA.4 RTM for the AMC566
  • DESY D1.4 Specification
  • 4x TI ADS42JB69
  • Total of 8 ADC 16-bit @ 250MSPS
  • Clock input for synchronization
View product MRT566A Data Sheet

MRT577A

MTCA.4 RTM for AMC577

  • MicroTCA.4 RTM for the AMC577
  • 16 ADC and input via Balun
  • 16 DAC as output via Balun
View product MRT577A Data Sheet

AMC522

MTCA.4 AMC Dual DAC, 16-bit @ 250 MSPS

  • Dual channel DAC 16-bit @ 250 MSPS (MAX5878)
  • Compliant to MTCA.4, double module, mid-size (full-size optional) with rear I/O
  • Xilinx Kintex-7 FPGA
  • Dual PCIe x4 or PCIe x8
  • JTAG interface port
  • AMC.1, AMC.2, AMC.4 compliant (FPGA programmable)
  • IPMI v2.0 compliant
View product AMC522 Data Sheet

MRT522

MTCA.4 RTM for AMC522

  • Double module, mid-size (full-size optional)
  • Two analog outputs from AMC522’s DACs via SSMC connectors
  • Eight analog inputs (AC or DC coupled) via SSMC connectors feeding on-board ADCs via programmable gain amplifiers JTAG interface port
  • Clocks and Trigger In/Out accessible via  Mini-display Port connectors
  • IPMI v2.0 compliant
View product MRT522 Data Sheet

MRT520

MicroTCA.4 RTM for AMC520

  • MicroTCA.4 RTM for the AMC520
  • Two analog outputs from AMC520’s DACs via SSMC connectors
  • Ten analog inputs (AC or DC coupled) interfacing directly with AMC520’s ADC ICs via SSMC connectors
  • Twelve LVDS signals and three differential reference clock routing to AMC520’s FPGA
  • LVDS and reference clocks accessible via dual high density DensiShield connectors
  • Double module, mid-size (full-size optional)
  • RoHS compliant
View product MRT520 Data Sheet

AMC521

24 Channels ADC, Mixed Sampling Rate

  • Sixteen channel of TI ADS42JB69 ADC 16-bit @ 250 MSPS
  • Eight channel SAR TI ADS8568 ADC 16-bit @ 650 KSPS simultaneous
  • Interface to the FPGA via JESD204B
  • 24 LVDS for Clock/Trig and/or GPIO
  • Virtex-7 FPGA 415T or 690T in FFG1158
  • Internal/External clock
  • Clock Jitter Cleaner with Dual Loop PLLs
  • Trig In/Out
  • A/D input via SSMC connectors
View product AMC521 Data Sheet

AMC520

AMC 10-channel ADC, MicroTCA.4

  • Double module AMC, compliant to μTCA.4
  • Ten channel of ADC with 125MSPS @ 16-bit resolution utilizing AD9268 device
  • Dual DAC with 250 MSPS @ 16-bit resolution utilizing MAX5878 device (this is user programmable for lower sampling rate)
  • Internal clock or precision external clock from RTM/backplane/front panel clocks
  • Trig in/out configurable by software (external trigger via front or port 17)
  • Backplane PCIe Dual x4 or x8/Dual GbE
  • Xilinx Virtex-6 FPGA in FF1759 package
  • Option for QDR-II+
  • AMC FCLKA, TCLKA, TCLKB, TCLKC and TCLKD are routed
  • Dual SFP+ (up to 6.6Gbps)
  • JTAG selectable front and backplane
  • AMC.1 and AMC.2 (FPGA programmable)
View product AMC520 Data Sheet

MicroTCA.4 AD/DA

( expand all )

MRT523

MTCA.4 RTM for AMC523, 12 Ch ADC 16-bit @ 125 MSPS

AMC523

Dual DAC 16-bit @ 250 MSPS, Kintex-7, MTCA.4

MRT575A

MTCA.4 RTM for AMC575, Passive

MRT566A

MTCA.4 RTM for AMC566

MRT577A

MTCA.4 RTM for AMC577

AMC522

MTCA.4 AMC Dual DAC, 16-bit @ 250 MSPS

MRT522

MTCA.4 RTM for AMC522

MRT520

MicroTCA.4 RTM for AMC520

AMC521

24 Channels ADC, Mixed Sampling Rate

AMC520

AMC 10-channel ADC, MicroTCA.4