AMC540

Xilinx Virtex-7 FPGA AMC with Dual TI DSP

  • Xilinx Virtex-7 XC7VX690T FPGA
  • DDR3 Memory (3 banks of 64-bit, 6 GB Total)
  • Dual DSP (TMS320C6678)
  • 8 GB of DDR3 per CPU with ECC
  • 24 TX/RX Fibre via MTP/MPO Connector
  • PCIe (AMC.1) and SRIO (AMC.4) on Ports 4-7 and 8-11 per FPGA load
  • GbE on Ports 0,1 (AMC.2)
  • Ports 12-15 and 17-20 routed to FPGA
  • Layer two managed switch

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The AMC540 incorporates the Xilinx Virtex-7 XC7VX690T FPGA. This re-configurable FPGA connects directly to the backplane allowing the core to interface to a host with multiple protocols such as 10GbE, PCIe or SRIO. Dual multicore Digital Signal Processors (DSP) TMS320C6678 connect to the FPGA via PCIe x2, and SRIO x4. The FPGA also interfaces to the AMC FCLKA and TCLKA-D via a clock and jitter cleaner, and has three external banks of 64-bit DDR3 memory.

The unit routes GbE on Ports 0 and 1 per AMC.2, PCIe Gen3/SRIO/10GbE dual x4 or single x8 on Ports 4-11 per AMC.1/ AMC.2/ AMC.4 specifications. Ports 12-15 and 17-20 are also routed to the FPGA.

An onboard managed Layer two switch interconnects the DSP, FPGA and external GbE (front panel, and rear Ports 0/1), supporting flexible signal processing applications.

 

Key Features
  • Xilinx Virtex-7 XC7VX690T FPGA
  • DDR3 Memory (3 banks of 64-bit, 6 GB Total)
  • Dual DSP (TMS320C6678)
  • 8 GB of DDR3 per CPU with ECC
  • 24 TX/RX Fibre via MTP/MPO Connector
  • PCIe (AMC.1) and SRIO (AMC.4) on Ports 4-7 and 8-11 per FPGA load
  • GbE on Ports 0,1 (AMC.2)
  • Ports 12-15 and 17-20 routed to FPGA
  • Layer two managed switch
Benefits
  • FPGA/DSP combination provides dense signal processing
  • Hyperlink provides tight coupling between DSP processors
  • Design utilizes proven VadaTech subcomponents and engineering techniques
  • Electrical, mechanical, software, and system-level expertise in house
  • Full system supply from industry leader
  • AS9100 and ISO9001 certified company
Specifications
Specifications

Block diagram

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