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Xilinx Zynq UltraScale+ FPGA with TCI6638 Multicore DSP+ARM, AMC

  • Xilinx Zynq®UltraScale+™ XCZU19EG FPGA Multi Processor System on Chip (MPSoC)
  • TCI6638K2K Multicore DSP+ARM® KeyStone II System-on-Chip (SoC)
  • Dual bank of DDR-4 64-bit wide with ECC to FPGA/SOC (16 GB total)
  • Dual banks of DDR3 64-bit wide with ECC to TCI6638 (16 GB total)
  • 3 SFP+ connectors to the front panel
  • PCIe (AMC.1), 10/40GbE (AMC.2), SRIO (AMC.4) capability on ports 4-7 (x4) and 8-11 (x4) per FPGA load
  • SRIO x4 to DSP via MUX selection
  • GbE on ports 0,1 (AMC.2)

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The AMC541 is based on Xilinx Zynq Ultrascale+ XCZU19EG MPSoC FPGA with embedded Quad-core ARM Cortex-A53 application processing unit, Dualcore ARM Cortex-R5 real-time processing unit, ARM Mali - MP2 GPU. The FPGA has Dual banks of 64-bit DDR4 memory (one bank to the ARM Core and one bank to the FPGA) and includes an SD card.

The AMC541 has the TCI6638K2K communications infrastructure KeyStone SoC which is a member of the C66x family based on TI’s new KeyStone II Multicore SoC Architecture designed specifically for high-performance telecommunication, IoT and networking applications. It features eight TMS320C66x DSP core subsystems (C66x CorePacs). The TMS320C66x interfaces to dual 64-bit wide DRAM DDR-3.

The flexible architecture including multiplexer allows the FPGA and DSP to interface to the AMC connector in different configurations. The AMC connector ports 2-3 and 8-11 are linked directly to the FPGA for the core to interface with the host through multiple protocols such as SRIO, PCIe or 10/40GbE. The ports 4-7 can connect directly to the FPGA in addition to ports 8-11 or connect directly to the DSP with SRIO protocol via MUX selection (DIP-switch selection).

The module also routes GbE on ports 0 and 1 per AMC.2. The DSP and FPGA are linked via PCIe x2 and GbE.

The on-board, re-configurable FPGA interfaces to the AMC FCLKA (fabric clock) and TCLKA-D (user clocks and triggers) via a clock and jitter cleaner. The module also has a front panel TRIG IN and CLK IN to the clock and jitter cleaner.

The front panel SFP+ cage allow expansion via fiber 1/10GbE or 1/10GbE copper interface.

Key Features
  • Xilinx Zynq®UltraScale+™ XCZU19EG FPGA Multi Processor System on Chip (MPSoC)
  • TCI6638K2K Multicore DSP+ARM® KeyStone II System-on-Chip (SoC)
  • Dual bank of DDR-4 64-bit wide with ECC to FPGA/SOC (16 GB total)
  • Dual banks of DDR3 64-bit wide with ECC to TCI6638 (16 GB total)
  • 3 SFP+ connectors to the front panel
  • PCIe (AMC.1), 10/40GbE (AMC.2), SRIO (AMC.4) capability on ports 4-7 (x4) and 8-11 (x4) per FPGA load
  • SRIO x4 to DSP via MUX selection
  • GbE on ports 0,1 (AMC.2)
Benefits
  • MPSoC FPGA and SoC DSP+ARM combination provides dense signal processing
  • Electrical, mechanical, software, and system-level expertise in house
  • Full system supply from industry leader
  • AS9100 and ISO9001 certified company
Specifications
Specifications

Block diagram

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