Single SERDES Input/Output with Clock Input

  • DP0 single SERDES RX+/- and TX+/- routed to the front
  • Direct Clock input to GBTCLK0 and GBTCLK1
  • SSMC connector for RX/TX pair and the clock input

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The FMC111 is an FPGA Mezzanine Card (FMC) per VITA 57.1 standard. The unit has a small footprint that enables the DP0 pairs to be accessed directly via SSMC connectors. A sinewave clock input can be used as a differential to the GBTCLK0+/- and GBTCLK1+/-.

Key Features
  • DP0 single SERDES RX+/- and TX+/- routed to the front
  • Direct Clock input to GBTCLK0 and GBTCLK1
  • SSMC connector for RX/TX pair and the clock input
Benefits
  • For Testing and direct coupled SERDES
  • Electrical, mechanical, software, and system-level expertise in house
  • Full system supply from industry leader
  • AS9100 and ISO9001 certified company
Specifications
Specifications

Block diagram

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