Description
The PCI594 is based on the Xilinx VU13P UltraScale+TM FPGA, which provides over 12,000 DSP slices, 360 Mb of UltraRAM and 3,780K logic cells. The FPGA interfaces to the quad QSFP28 modules. It also has interface to a single DDR4 memory bank that is 64-bit wide with16 GB total. This allows for large buffer sizes to be stored during processing as well as for queuing the data to the host.
PCI594 has a PLL that can lock into an external clock such as 1PPS or to a sinewave clock up to 400MHz. The module also has a GbE with SyncE capabilities. The PCI594 could run as SyncE Master and/or Slave. The module provides four clock output which could be connected to adjacent PCI594 modules to allow synchronized between modules.
PCI594 has x16 PCIe edge connector routed to the FPGA PCIe hard IP block. The x16 SERDES going to the edge connector could be configured to run any protocol and integrated, for example, into VadaTech’s VT808 chassis. In addition, there are 16 uncommitted SERDES routed to a dual x8 expansion connector, providing direct connectivity to a neighboring FPGA (e.g. via Aurora, 10/40GbE, SRIO, PCIe) without the need to go through the host.
The Quad QSFP28 Cages could take 100GbE as well as 40GbE optical transceiver. The optical modules could be bifurcated to Quad 1/10/25GbE lanes for a total of 16 ports. The optical modules are protocol agnostic and could take a mix of 100G and/or 40G transceiver.
Active cooling of the module and option with passive cooling. The passive cooling requires a chassis that forces air over the PCI594 heat sink, such as VadaTech’s VT808 chassis.
