SOFI Overview

SOFI Module ConceptThe Serial Optimized FPGA Interface (SOFI) module concept is proprietary to VadaTech. It supports rapid product development but is not intended for field interoperability. Key characteristics of this approach are as follows:

  • Makes use of FMC physical form factor but is not compatible with FMC carriers.Re-purposes pins on the mezzanine interface connector to support many more SERDES connections. This allows the mezzanine to provide more ADC/DAC with JESD connections to the FPGA.
  • Achieves higher SERDES count without the need for secondary connector, so making it suitable on compact form factor products (e.g. AMCs and 3U VPX modules).
  • The SOFI module concept can be used in conduction cooled products.
  • Some SOFI modules include a daughter-card assembly for even higher performance density. Such modules may be limited in temperature range supported. Check with VadaTech sales for details.
  • SOFI modules are compatible with SOFI carriers in various form factors, allowing rapid porting of designs from commercial to mil/aero products.

Each combination of SOFI module and carrier requires engineering development in thermal design, board support package and reference design firmware. This datasheet summarizes the SOFI/carrier combinations currently available. Contact your local VadaTech sales team for the latest information if a required combination is not listed here.

Key Features
Benefits
Related Products

AMC599

Dual ADC @ 10.4 or 6.4 GSPS and Dual DAC @ 12 GSPS, UltraScale, AMC

  • Xilinx UltraScale™ XCKU115 FPGA
  • Dual ADC 12-bit @ 10.4/6.4 GSPS or quad ADC @ 5.2/3.2 GSPS with TI ADC12DJ5200 or ADC12DJ3200
  • Option for ADC12DJ5200, ADC12DJ3200 or ADC12DJ2700
  • Dual DAC 16-bit @12 GSPS (AD9162 or AD9164)
  • Two banks of 64-bit wide and a single bank of 32-bit wide DDR4 for a total of 20 GB
  • AMC Ports 4-11 are routed to FPGA per AMC.1, AMC.2 and AMC.4 (protocols such as PCIe, SRIO, 1/10/40GbE, etc. are FPGA programmable)
  • AMC FCLKA, TCLKA, TCLKB, TCLKC and TCLKD are routed
  • Clock jitter cleaner
  • IPMI 2.0 compliant
View product AMC599 Data Sheet

VPX599

Dual ADC @ 10.4 or 6.4 GSPS and Dual DAC @ 12 GSPS, UltraScaleā„¢, 3U VPX

  • 3U FPGA Dual ADC and Dual DAC per VITA 46
  • Xilinx Kintex UltraScale™ XCKU115 FPGA
  • Dual ADC 12-bit @ 10.4/6.4 GSPS or quad ADC @ 5.2/3.2 GSPS with TI ADC12DJ5200 or ADC12DJ3200
  • Option for ADC12DJ5200, ADC12DJ3200 or ADC12DJ2700
  • Dual DAC 16-bit @ 12 GSPS (AD9162 or AD9164) or TI DAC38RF82 14-bit @ 9GSPS
  • High-performance clock jitter cleaner
  • VHDL reference design with source code
  • Protocols such as PCIe, SRIO, 10GbE/40GbE, etc. are FPGA programmable
  • 16 GB of DDR4 Memory (64-bit wide)
  • Health Management through dedicated Processor
View product VPX599 Data Sheet

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