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FMC235

Quad ADC 16-bit @ 250 MSPS, Single DAC 14-bit 500 @ MSPS

  • Dual ADS42JB69 (Quad ADC in total), 16-bit @ 250MSPS
  • JESD204B lanes from each ADC
  • Single DAC3171 (LVDS Based), 14-bit @ 500MSPS
  • Front end RF is DC coupled for the ADC and the DAC
  • Excellent dynamic performance
  • Front panel interface includes CLK In, Trig In and Trig Out

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The FMC235 is an FPGA Mezzanine Card (FMC) per VITA 57.1 specification. The board has Quad ADC and single DAC with DC coupled Input and Output.

The FMC235 utilizes dual ADS42JB69 ADCs which provides quad ADC 16‑bit conversion at rates of up to 250 MSPS, and a single DAC3171 providing 14-bit conversion at rates of up to 500MSPS.

The analog input, digital output, clock and trigger interfaces of the FMC235 are routed via SSMC connectors. The internal clock frequency is programmable and the clock is capable of locking to an external reference.

Key Features
  • Dual ADS42JB69 (Quad ADC in total), 16-bit @ 250MSPS
  • JESD204B lanes from each ADC
  • Single DAC3171 (LVDS Based), 14-bit @ 500MSPS
  • Front end RF is DC coupled for the ADC and the DAC
  • Excellent dynamic performance
  • Front panel interface includes CLK In, Trig In and Trig Out
Benefits
  • Ideal for Broadband communications systems, Wireless infrastructure, LTE, ATE, RADAR / Jamming
  • Compatible with a broad range of Xilinx and Altera based FMC carriers from VadaTech and others
  • Electrical, mechanical, software, and system-level expertise in house
  • Full system supply from industry leader
  • AS9100 and ISO9001 certified company
Specifications
Specifications

Block diagram

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