Key Features
Related Products


Altera Carrier for FMC, Stratix® V (5SGXEA)

  • Single module, mid-size or full-size
  • AMC FPGA based on Altera Stratix® V (5SGXEA) in F1932 package
  • VITA 57.1 FMC HPC Connector (compatible with LPC)
  • AMC Ports 0-15, 17-20 and FMC Ports DP0-9 are routed for high speed SERDES protocols
  • All FMC LA, HA, HB pairs routed bi-directionally
  • High-speed SERDES protocols such as PCIe x4, SRIO, XAUI, 1000Base-X are FPGA programmable
  • Onboard PLL for buffering/multiplying and jitter cleaner (Stratum-3)
  • M-LVDS/LVDS Clock crossbar switch for flexible clock routing
  • 4 GB of DDR3 memory to FPGA (4 channels x 1 GB each)
  • Serial Over LAN (SOL) with hardware RNG
View product AMC532 Data Sheet


FMC Dual ADC, 12-bit @ 2.6 GSPS with single DAC 14-bit @ 5.7GSPS

  • Dual AD9625 ADC
    • 4/6 JESD204B lanes from the ADC is routed to the FMC
    • 12-bit @ 2.6 GSPS
    • Wide full power bandwidth supports IF sampling of signals up to 2 GHz
  • Single DAC AD9129 
    • 14-bit @ 5.7 GSPS
  • FPGA Mezzanine Card (FMC) per VITA 57
  • Excellent dynamic performance
  • Front panel interface includes CLK In, Trig In and Trig Out
View product FMC227 Data Sheet


3rd Gen MicroTCA Carrier Hub (MCH), 40GbE/PCIe Gen 3


  • Unified 1GHz quad-core CPU for MCMC (MicroTCA Carrier Management Controller), Shelf Manager, Clocking, and Fabric management
  • Automatic fail-over with redundant UTC004s
  • 1GbE base switch with dual 100/1000/10G uplink
  • Full Layer 3 managed Ethernet switches
  • Non-blocking PCIe Gen 3, SRIO Gen 2, 10GbE/40GbE, or Crossbar Switch option to AMC fat pipes with options for up to 40GbE uplink
  • Low-jitter M-LVDS clock distribution crossbar matrix
  • PLL synthesizer for generating any clock frequency disciplined to GPS/SyncE/IEEE1588
  • Single module, full size per AMC.0
View product UTC004 Data Sheet

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