FMC+ Dual CXP Connectors

  • FPGA Mezzanine Card (FMC+) per VITA 57.4
  • Single module
  • Dual CXP style connector
  • Six distinct oscillators to allow maximum flexibility per x4 lane speed

Download Datasheet Add to Info Request

add to compare

The FMC100 is an FMC+ module with two CXP style connectors on the front panel. The module routes 24 pairs of high-speed signals from the FMC+ connector to the CXP connectors.

The FMC100 has six oscillators onboard which provide SERDES clock to each quad sector. This allows each x4 lanes to have its own clock for maximum flexibility.

Due to the height of the CXP connector (which is beyond 10mm), the module has a 17mm stack height connector. While the module will mate to a standard FMC+ carrier, the front panel of the carrier must be designed to accommodate this height difference.

Key Features
  • FPGA Mezzanine Card (FMC+) per VITA 57.4
  • Single module
  • Dual CXP style connector
  • Six distinct oscillators to allow maximum flexibility per x4 lane speed
  • Design utilizes proven VadaTech subcomponents and engineering techniques
  • Electrical, mechanical, software, and system-level expertise in house
  • Full ecosystem of front and rear boards, enclosures, specialty modules, and test/dev products from one source
  • AS9100 and ISO9001 certified company

Block diagram

Related Products


Kintex-7 FPGA Carrier for FMC, AMC

  •  AMC FPGA carrier for FMC per VITA 57
  • Xilinx Kintex-7 410T FPGA in FFG-900 package with optional P2040
  • Supported by DAQ Series™ data acquisition software
  • AMC Ports 4-11 are routed to FPGA per AMC.1, AMC.2 and AMC.4 (protocols such as PCIe, SRIO, XAUI, etc. are FPGA programmable)
  • Single module, mid-size AMC (full-size optional)
  • Clock jitter cleaner
  • IPMI 2.0 compliant
View product AMC517 Data Sheet


Altera Carrier for FMC, Stratix® V (5SGXEA)

  • Single module, mid-size or full-size
  • AMC FPGA based on Altera Stratix® V (5SGXEA) in F1932 package
  • VITA 57.1 FMC HPC Connector (compatible with LPC)
  • AMC Ports 0-15, 17-20 and FMC Ports DP0-9 are routed for high speed SERDES protocols
  • All FMC LA, HA, HB pairs routed bi-directionally
  • High-speed SERDES protocols such as PCIe x4, SRIO, XAUI, 1000Base-X are FPGA programmable
  • Onboard PLL for buffering/multiplying and jitter cleaner (Stratum-3)
  • M-LVDS/LVDS Clock crossbar switch for flexible clock routing
  • 4 GB of DDR3 memory to FPGA (4 channels x 1 GB each)
  • Serial Over LAN (SOL) with hardware RNG
View product AMC532 Data Sheet


FMC ADC 10-bit @ 2.6 GSPS Module

  • FPGA Mezzanine Card (FMC) per VITA-57
  • Single ADC EV10AS150B @2.5 GSPS
  • Single module
  • 5 GHz Full Power Input Bandwidth (-3dB)
  • True single core architecture (no calibration required)
  • External Interleaving:Full scale analog input Voltage Span 500mVpp
    • Gain Adjust
    • Offset Adjust
    • Sampling Delay Adjust
  • All front panel input/outputs are via MMCX:
    • Analog Input
    • Reference clock
    • Trig in/out
    • General purpose I/O
  • Super low phase noise RF PLL Synthesizer
View product FMC210 Data Sheet

Info request

Create a list of products to inquire about for more information or quote request.